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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc34701 rev 7.0, 8/2007 freescale semiconductor technical data ? freescale semiconductor, in c., 2007. all rights reserved. 1.5a switch-mode power supply with linear regulator the 34701 provides the means to efficiently supply the freescale power quicc? i, ii, and other families of freescale microprocessors and dsps. the 34701 incorporates a high performance switching regulator, providing the direct supply for the microprocessor?s core, and a low dropout (ldo) linear regulator control circuit provides the micr oprocessor i/o and bus voltage. the switching regulator is a hi gh-efficiency synchronous buck regulator with integrated n-channel power mosfets to provide protection features and to allow space-efficient, compact design. the 34701 incorporates many advan ced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and prot ection of the cpu and power system. features ? operating voltage from 2.8v to 6.0v ? high-accuracy output voltages ? fast transient response ? switcher output current up to 1.5a ? under-voltage lockout and overcurrent protection ? enable inputs and programmable watchdog timer ? voltage margining via i 2 c? bus ? reset with programmable power-on delay ? pb-free packaging designated by suffix code ew i 2 c is a trademark of philips corporation. figure 1. 34701 simplified application diagram power supply 34701 ordering information device temperature range (t a ) package MCZ34701ew/r2 -40 to 85c 32 soicw ew (pb-free) suffix 98aarh99137a 32-pin soicw other circuits rt vbd vddh (i/os) vddl (core) mpc8xxx 34701 2.8 v to 6.0 v input vin2 clksel freq poreset gnd sda scl adjustable: 0.8 v to vin - dropout addr vin1 ldrv ldo lfb cs rst sw pgnd inv vbst boot vout clksyn optional en1 en2 vbst adjustable: 0.8 v to vin - dropout vddi
analog integrated circuit device data 2 freescale semiconductor 34701 internal block diagram internal block diagram figure 2. 34701 simplifi ed internal block diagram vin1 vbst vbd vin vddi internal supply boost control bandgap voltage reference en1 en2 rt a ddr sda scl rst power sequencing voltage margining watchdog timer reset control por timer buck control logic buck hs and ls driver thermal limit i 2 c interface switcher oscillator 300 khz ramp gen. uvlo linear regulator control i lim + - + - + - vbst v ref v ref v ref v ref vbst vbst vbst vddi vddi vddi vddi vddi vddi ldrv cs ldo lfb lcmp boot sw vin2 pgnd inv vout gnd freq clksyn clksel (4) (2) (2) (2) 8.0 v 0.8 v reset power enable syscon i 2 c control syscon softst power down current limit pwm comp error amp vldo vout to reset control vout power seq power seq i 2 c control q1 q2 inv lfb q3 q4 to reset control q5 q6
analog integrated circuit device data freescale semiconductor 3 34701 pin connections pin connections figure 3. pin connections table 1. pin function description a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin pin name formal name definition 1 freq oscillator frequency this switcher frequency selection pin can be adjusted by connecting external resistor rf to the freq pin. the default switching frequency (freq pin left open or tied to vddi) is set to 300khz. 2 inv inverting input buck controller error amplifier inverting input. 3 vout output voltage output voltage of the buck converter. input pin of the switching regulator power sequence control circuit. 4, 5 vin2 input voltage 2 buck regulator power input. drain of the high side power mosfet. 6, 7 sw switch buck regulator switching node. this pin is connected to the inductor. 8, 9 24, 25 gnd ground analog ground of the ic, thermal heatsinking. 10, 11 pgnd power ground buck regulator power ground. 12 vbd boost drain drain of the internal boost regulator power mosfet. 13 vbst boost voltage internal boost regulator output voltage. the internal boost regulator provides a 20ma output current to supply the drive circuits for the integrated power mosfets and the external n-channel power mosfet of the linear regulator. the voltage at the vbst pin is 7.75v (nominal). 14 boot bootstrap bootstrap capacitor input. 15 sda serial data i 2 c bus pin. serial data. 16 scl serial clock i 2 c bus pin. serial clock. 17 lcmp linear compensation linear regulator compensation pin. 18 lfb linear feedback linear regulator feedback pin. 19 ldo linear regulator input pin of the linear regulat or power sequence control circuit. clksyn 1 en2 en1 addr gnd gnd v dd1 v in1 ldrv cs lfb lcmp ldo rt clksel rst freq v in2 sw sw gnd gnd pgnd pgnd vbd vbst sda scl boot v in2 inv v out 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31
analog integrated circuit device data 4 freescale semiconductor 34701 pin connections 20 cs current sense current sense pin of the ldo. over-current protection of the linear regulator external power mosfet. the voltage drop over the ld o current sense resistor rs is sensed between the cs and ldo pins. the ldo curr ent limit can be adjusted by selecting the proper value of the current sensing resistor rs. 21 ldrv linear drive ldo gate drive of the external pass n-channel mosfet. 22 vin1 input voltage 1 the input supply pin for the integrated circ uit. the internal circuits of the ic are supplied through this pin. 23 vddi power supply internal supply voltage. a ceramic low esr 1uf 6v x5r or x7r capacitor is recommended. 26 addr address i 2 c address selection. this pin can either be left open, tied to vddi, or grounded through a 10k ? resistor. 27 en1 enable 1 enable 1 input. the combination of the logic state of the enable 1 and enable 2 inputs determines operation mode and type of power sequencing of the ic. 28 en2 enable 2 enable 2 input. the combination of the logic state of the enable 1 and enable 2 inputs determines operation mode and type of power sequencing of the ic. 29 rt reset timer this pin allows programming of the power-o n reset delay by means of an external rc network. 30 rst reset output (active low) the reset control circuit monitors both t he switching regulator and the ldo feedback voltages. it is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the ldo) by an external resistor. 31 clksel clock selection this pin sets the clksyn pin as either an oscillator output or a synchronization input pin. the clksel pin is also used for the i 2 c address selection. 32 clksyn clock synchronization oscillator output/synchronization input pin. table 1. pin function description (continued) a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin pin name formal name definition
analog integrated circuit device data freescale semiconductor 5 34701 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. rating symbol value unit electrical ratings supply voltage v in1 , v in2 -0.3 to 7.0 v switching node voltage v sw -1.0 to 7.0 v buck regulator bootstrap input voltage (boot - sw) v in(boot) -0.3 to 8.5 v boost regulator output voltage v bst -0.3 to 8.5 v boost regulator drain voltage v bd -0.3 to 9.5 v rst drain voltage v rst -0.3 to 7.0 v enable pin voltage at en1, en2 v en -0.3 to 7.0 v logic pin voltage at sda, scl v log -0.3 to 7.0 v analog pin voltage ldo, vout, rst ldrv, lcmp, cs v out v lin -0.3 to 7.0 -0.3 to 8.5 v pin voltage at clksel, addr, rt, freq, vddi, clksyn, inv, lfb v logic -0.3 to 3.6 v esd voltage (1) human body model machine model v esd 2000 200 v notes 1. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ), and the charge device model.
analog integrated circuit device data 6 freescale semiconductor 34701 electrical characteristics maximum ratings thermal ratings storage temperature t stg -65 to 150 c peak package reflow temperature during reflow (2) , (3) t pprt note 3 c maximum junction temperature t jmax 125 c thermal resistance junction to ambient (single layer) (4) , (5) junction to ambient (four layers) (4) , (5) r ja 70 55 c/w thermal resistance, junction to base (6) r jb 18 c/w operational package temperature (ambient temperature) t a -40 to 85 c notes 2. pin soldering temperature limit is for 10 seconds maximum du ration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 3. freescale?s package reflow c apability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 4. junction temperature is a function of on-chip power dissipation, package thermal re sistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance. 5. per jedec jesd51-6 with the board horizontal 6. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. rating symbol value unit
analog integrated circuit device data freescale semiconductor 7 34701 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figure 33 ), unless otherwise noted. characteristic symbol min typ max unit general operating voltage range (vin1, vin2) v in 2.8?6.0v start-up voltage threshold (boost switching) v st ?1.61.8v vbst under-voltage lockout (vbst rising) v bst_uvlo 5.5?6.5v vbst under-voltage lockout hysteresis v bst_uvlo_hys 0.5?1.5v input dc supply current (normal operation mode, enabled), unloaded outputs i in ?60?ma vin1 pin input supply current (en1 = en2 = 0) i in1 ?10?ma vin2 pin input leakage current (en1 = en2 = 0) i in2 ? 100 ? a vddi internal supply voltage v ddi 2.9?3.3v vddi maximum output current (externally loaded) i ddi ??-10ma buck converter buck converter feedback voltage (7) , (8) ivout = 15ma to 1.5a. includes load regulation error v inv 0.784 0.800 0.816 v buck converter voltage margining step size v mvo ?1.0?% buck converter voltage margining highest positive value v mp 5.9?7.9% buck converter voltage margining lowest negative value v mn -7.9?-5.9% buck converter line regulation (7) , (8) vin1 = vin2 = 2.8v to 6.0v, ivout = 15ma to 1.5a reg lnvo -1.0 ? 1.0 % buck converter load regulation (7) , (8) vin1 = vin2 = 2.8v to 6.0v, ivout = 15ma to 1.5a reg ldvo -1.0 ? 1.0 % vout input leakage current vout = 5.25v i invout ?3.5? ma inv input leakage current inv = 0.8v i ininv -1.0 ? 1.0 a notes 7. design information only. this parameter is not production tested. 8. ivout refers to load current on output switcher.
analog integrated circuit device data 8 freescale semiconductor 34701 electrical characteristics static electrical characteristics buck converter (continued) high side power mosfet q1 rds(on) (9) , (10) id = 500ma, t a = 25c, vbst = 8.0v r ds(on)q1 ?60? m ? low side power mosfet q2 rds(on) (9) , (10) id = 500ma, t a = 25c, vbst = 8.0v r ds(on)q2 ?65? m ? buck converter peak curr ent limit (high level) i limh -4.0 -2.7 -1.5 a vout pull-down mosfet q3 current limit t a = 25c, vbst = 8.0v i limpq3 0.75 ? 2.0 a vout pull-down mosfet q3 r ds(on) (10) id = 1.0a, vbst = 8.0v r ds(on)pq3 ??1.9 ? thermal shutdown (vout pull-down mosfet q3) (9) t sd 150 170 190 c thermal shutdown hysteresis (9) t hys ?10?c notes 9. design information only. this parameter is not production tested. 10. id is the mosfet drain current. table 3. static electrical characteristics (continued) characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figure 33 ), unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 34701 electrical characteristics static electrical characteristics error amplifier (buck converter) input impedance (11) r in ? 500 ? k ? output impedance (11) r out ? 150 ? ? dc open loop gain (11) a vol ?80?db gain bandwidth product (11) g bw ?35?mhz slew rate (11) v sr ? 200 ? v/ s output voltage ? high level vin1 > 3.3v, ioea = -1.0ma (11) , (12) v ea_oh ?2.0? v output voltage ? low level ioea = -1.0 ma (11) , (12) v ea_ol ?0.4? v oscillator ramp (11) v scramp ?0.5?v oscillator clksyn pin (open) low level output voltage iol = +1.0ma (13) v osc_ol ??0.4v clksyn pin (open) high level output voltage ioh = -1.0ma (14) v osc_oh v ddi -0.4v ? ? v clksyn pin (grounded) input voltage threshold v osc_ih 1.2?2.0v clksyn pin pull-up resistance r pu 60 ? 240 k ? frequency adjusting reference voltage v freq ?1.26?v boost regulator regulator output voltage ibst = 20ma, vin1 = vin2 = 2.8v to 6.0v v bst 7.3 7.7 8.3 v power mosfet q5 rds(on) (11) ibd = 500ma, t a = 25c r ds(on)q5 ? 650 1000 m ? regulator recommended output capacitor c bst ?10? f regulator recommended output capacitor maximum esr esrc bst ? 100 ? m ? notes 11. design information only. this parameter is not production tested. 12. ioea refers to error amplifier output current. 13. iol refers to i/o low level 14. ioh refers to i/o high level table 3. static electrical characteristics (continued) characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figure 33 ), unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 34701 electrical characteristics static electrical characteristics linear regulator (ldo) ldo feedback voltage (16) vin1 = vin2 = 2.8v to 6.0v, ildo = 10ma to 1000ma. includes load regulation error v lfb 0.784 0.800 0.816 v ldo voltage margining step size v mldo ?1.0?% ldo voltage margining highest positive value v mp 5.9?7.9% ldo voltage margining lowest negative value v mn -7.9?-5.9% ldo line regulation (16) vin1 = vin2 = 2.8v to 6.0v, ildo = 1000ma reg lnvldo -1.0 ? 1.0 % ldo load regulation (16) ildo = 10ma to 1000ma reg ldvldo -1.0 ? 1.0 % ldo ripple rejection, dropout voltage (16) vdo = 1.0v, vripple = +1.0v p-p sinusoidal, f = 300khz, ildo = 500ma (15) v ldo_rr ?40? db ldo maximum dropout voltage (vin - vldo), using irl2703 (16) vldo = 2.5v, ildo = 1000ma v do ?5075 mv ldo current sense comparator threshold voltage (vcs - vldo) v csth 35 50 65 mv ldo pin input current, vldo = 5.25v i ldo 1.0 1.9 4.0 ma ldo feedback input current (lfb pin), vlfb = 0.8v i lfb -1.0 ? 1.0 a ldo drive output current (ldrv pin), vldrv = 0v i ldrv -5.0 -3.3 -2.0 ma cs pin input leakage current vcs = 5.25v i cslk 50 ? 200 a ldo pull-down mosfet q4 current limit t a = 25c, vbst = 8.0v (ldo pin) i limq4 0.75 ? 2.0 a ldo pull-down mosfet q4 rds(on) id = 1.0a, vbst = 8.0v r ds(on)q4 ??1.9 ? ldo recommended output capacitance c ldo ?10? f ldo recommended output capacitor esr r ldo ?5.0?m ? thermal shutdown (ldo pull-down mosfet q4) (15) t sd 150 170 190 c thermal shutdown hysteresis (15) t sdhys ?10?c notes 15. design information only. this parameter is not production tested. 16. ido refers to load current on external ldofet - irl2703 is the intersil mosfet. table 3. static electrical characteristics (continued) characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figure 33 ), unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 34701 electrical characteristics static electrical characteristics control and supervisory circuits enable (en1, en2) input voltage threshold v en-th 1.0 1.5 2.0 v enable (en1, en2) pull-down resistance r en-pd 30 55 90 k ? rst low-level output voltage, iol = 5.0ma v ol ??0.4v rst leakage current, off state, pulled up to 5.25v i lkg-rst ??10 a rst under-voltage threshold on vout ( ? vout/vout ) (17) v outi th -14 ? -0.5 % rst over-voltage threshold on vout ( ? vout/vout ) (17) v outi th 0.5 ? 14 % rst under-voltage threshold on vldo ( ? vldo/vldo ) (17) v ldoi th -12 ? -4.0 % rst over-voltage threshold on vldo ( ? vldo/vldo ) (17) v ldoi th 4.0 ? 12 % rst timer voltage threshold v th-rt 1.0 1.2 1.5 v rst timer source current (rt pin at 0v) i s-rt -17?-34ma rst timer leakage current i lkg-rt -1.0 ? 1.0 a rst timer saturation voltage, reset timer current = 300 av sat-rt ? 35 100 mv maximum recommended value of the reset timer capacitor c t ??47 f clksel threshold voltage v thclks 1.2 1.6 2.0 v clksel pull-up resistance r pu-clk s 60 120 240 k ? addr threshold voltage (17) v thaddr 1.2 1.6 2.0 v addr pull-up resistance r pu-addr 60 120 240 k ? thermal shut-down (ic sensor) (17) t lim 150 170 190 c thermal shut-down hysteresis (17) t limhys ?10?c sda, scl pins i 2 c bus (standard) input threshold voltage (pin scl), rising edge (17) v lth 1.3?1.7v input threshold voltage (pin sda) v lth 1.3?1.7v sda, scl input current, input voltage = 5.25v (vin1) i in ?1.010 a sda low-level output voltage, 3.0ma sink current v ol ??0.4v sda, scl capacitance (17) c input ? 7.0 10 pf notes 17. design information only. this parameter is not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figure 33 ), unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 34701 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figures 33 ), unless otherwise noted. characteristic symbol min typ max unit buck converter duty cycle range (normal operation) (18) t d 0.0 ? 95 % switching node sw rise time (18) vin = 5.0v, iload = 1.0a t rise ?7.0? ns switching node sw fall time (18) vin = 5.0v, iload = 1.0a t fall ?17? ns maximum deadtime (18) t d ?35?ns buck control loop propagation delay (18) vinv < 0.8v to vsw > 90% of high level or vinv > 0.8v to vsw < 10% of low level t pd ?50? ns soft start duration (power sequencing disabled, en1 = 1, en2 = 1) (18) t ss 200 350 800 s fault condition timeout (18) t fault 7.0 10 15 ms retry timer cycle (18) t ret 70 100 150 ms oscillator oscillator center frequency (20) rf = 11.3k ? f osc 270 300 330 khz oscillator frequency range f osc 200 ? 400 khz oscillator frequency adju sting resistor range r freq 7.0 ? 22 k ? oscillator frequency adjustment (19) , (20) rf = 7.0k ? f osc 400 ? ? khz oscillator frequency adjustment (19) , (20) rf = 22k ? f osc ? ? 200 khz oscillator default fr equency (switching frequency), freq pin open f osc ? 300 ? khz oscillator output signal duty cycle (square wave, 180 out-of-phase with the internal suitable oscillator) d osc 40 50 60 % synchronization pulse minimum duration (18) t sync 1.0 ? ? s notes 18. design information only. this parameter is not production tested. 19. see figure 4 for more details 20. rf is rfreq
analog integrated circuit device data freescale semiconductor 13 34701 electrical characteristics dynamic electrical characteristics boost regulator boost regulator mosfet maximum on time (21) t on ?24? s boost regulator control loop propagation delay (21) t bst_pd ?50?ns boost switching node vbd rise time (21) ibst = 20ma t b_rise ?5.0 ns boost switching node vbd fall time (21) ibst = 20ma t b_fall ?3.0? ns linear regulator (ldo) fault condition timeout t fault 7.0 10 15 ms retry timer cycle t ret 70 100 150 ms reset monitor ( rst ) monitoring lfb pin delay t d_rst_lfb 12?28 s monitoring inv pin delay t d_rst_inv 12?28 s sca, scl pin, i 2 c bus (standard) scl clock frequency (21) f scl ? ? 100 khz bus free time between a stop and a start condition (21) t buf 4.7 ? ? s hold time (repeated) start condition (after this period, the first clock pulse is generated.) (21) t hd-sta 4.0 ? ? s low period of the scl clock (21) t low 4.7 ? ? s high period of the scl clock (21) t high 4.0 ? ? s sda fall time from vih_max to vil_min, bus capacitance 10pf to 400pf, 3.0ma sink current (21) , (23) t f ? ? 250 ns setup time for a repeated start condition (21) t su-sta 4.7 ? ? s data hold time for i 2 c bus devices (21) , (22) t hd-dat 0.0 ? ? s data setup time (21) t su-da t 250 ? ? ns setup time for stop condition (21) t su-sto 4.0 ? ? s capacitive load for each bus line (21) c b ? ? 400 pf notes 21. design information only. this parameter is not production tested. 22. the device provides an internal hold time of at least 300ns for the sda signal (refer to the v ih_min of the scl signal) to bridge the undefined region of the falling edge of scl. 23. vih is high level voltage on i 2 c bus lines and vil is low level voltage on i 2 c bus lines table 4. dynamic electrical characteristics (continued) characteristics noted under conditions -40c t a 85 c unless otherwise noted. input voltages vin1 = vin2 = 3.3v using the typical application circuit (see figures 33 ), unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 34701 electrical characteristics timing diagram timing diagram figure 4. definition of time on the i 2 c bus electrical per formance curves figure 5. f osc vs. temperature figure 6. f osc vs. rf figure 7. switcher efficiency vs. load current figure 8. switcher i lim vs. temperature t su-sto t su-sta t su-dat t hd-dat t hd-sta t hd-sta 280 285 290 295 300 -50 0 50 100 temperature (c) fosc (khz) f osc (khz) 280 285 290 295 300 -50 0 50 100 temperature (c) fosc (khz) f osc (khz) temperature (c) 100 150 200 250 300 350 400 450 7121722 rf ( k oh m ) oscillator frequency (khz) f osc (khz) rf (k ? ) 0 1 0 20 30 40 50 60 70 80 90 1 00 00,5 11 ,5 load current [a] switcher efficiency [%] vin=3.3v, vout=1.2v vin=3.3v, vout=1.8v vin=5.0v, vout=1.2v vin=5.0v, vout=1.8v 2.00 2.20 2.40 2.60 2.80 3.00 -50050100 temperature (c) switcher i lim (a)
analog integrated circuit device data freescale semiconductor 15 34701 electrical characteristics electrical performance curves figure 9. v ref vs. temperature figure 10. timer (ms) vs. rt 0.77 0.78 0.79 0.80 0.81 0.82 0.83 -50 0 50 100 tem perature (c) vref (v) v ref (v) temperature (c) 5 7 9 11 13 15 17 19 21 23 25 0 100 200 300 rt (kohm) with ct = 33nf timer (ms) rt (k ? ) with ct = 33 nf
analog integrated circuit device data 16 freescale semiconductor 34701 functional description introduction functional description introduction the 34701 power supply integrated circuit provides the means to efficiently supply the freescale power quicc and other families of freescale microprocessors. it incorporates a high performance synchronous buck regulator, supplying the microprocessor?s core, and a low dropout (ldo) linear regulator providing the microprocessor i/o and bus voltages. this device incorporates m any advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the cpu and power system. at the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system. functional pin description oscillator frequency pin (freq) this switcher frequency selection pin can be adjusted by connecting external resistor rf to the freq pin. the default switching frequency (freq pin left open or tied to vddi) is set to 300khz. inverting input pin (inv) buck controller error amplifier inverting input. output voltage pin (vout) output voltage of the buck converter. input pin of the switching regulator power sequence control circuit. input voltage 2 pins (vin2) buck regulator power input. drain of the high side power mosfet. switch pins (sw) buck regulator switching node. this pin is connected to the inductor. ground pins (gnd) analog ground of the ic, thermal heatsinking. power ground pins (pgnd) buck regulator power ground. boost drain pin (vbd) drain of the internal boost regulator power mosfet. boost voltage pin (vbst) internal boost regulator output voltage. the internal boost regulator provides a 20ma output current to supply the drive circuits for the integrated power mosfets and the external n-channel power mosfet of the linear regulator. the voltage at the vbst pin is 7.75v nominal. bootstrap pin (boot) bootstrap capacitor input. serial data pin (sda) i 2 c bus pin. serial data. serial clock pin (scl) i 2 c bus pin. serial clock. linear compensation pin (lcmp) linear regulator compensation pin. linear feedback pin (lfb) linear regulator feedback pin. linear regulator pin (ldo) input pin of the linear regulator power sequence control circuit. current sense pin (cs) current sense pin of the ldo. over-current protection of the linear regulator external power mosfet. the voltage drop over the ldo current sense resistor rs is sensed between the cs and ldo pins. the ldo current limit can be adjusted by selecting the proper value of the current sensing resistor rs. linear drive pin (ldrv) ldo gate drive of the external pass n-channel mosfet. input voltage 1 pin (vin1) the input supply pin for the integrated circuit. the internal circuits of the ic are supplied through this pin.
analog integrated circuit device data freescale semiconductor 17 34701 functional description functional pin description power supply pin (vddi) internal supply voltage. a ceramic low esr 1uf 6v x5r or x7r capacitor is recommended. address pin (addr) the addr pin is used to set the address of the device when used in an i 2 c communication. this pin can either be tied to vddi or grounded through a 10k ? resistor. refer to i 2 c bus operation on page 26 for more information on this pin. enable 1 and 2 pins (en1 and en2) these two pins permit positive logic control of the enable function and selection of the power sequencing mode concurrently. table 5 depicts the en1 and en2 function and power sequencing mode selection. both en1 and en2 pins have internal pull-down resistors and both can withstand a short circuit to the supply voltage, 6.0v. reset timer pin (rt) the reset timer power-up delay (rt) pin is used to set the delay between the time when the ldo and switcher outputs are active and stable and the rst output is released. an external resistor and capacitor are used to program the timer. the power-up delay can be obtained by using the following formula: t d = 10ms + r t c t where r t is the reset timer programming resistor and c t is the reset timer programming capacitor, both connected in parallel from rt to ground. note observe the maximum c t value and expect reduced accuracy if r t is less than 10k ? . reset output pin ( rst ) the reset control circuit monitors both the switching regulator and the ldo feedback voltages. it is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the ldo) by an external resistor. the reset control circuit supervises both output voltages?the linear regulator output v ldo and the switching regulator output v out . when either of these two regulators is out of regulation (high or low), the rst pin is pulled low. there is a 20 s delay filter preventing erroneous resets. during power-up sequencing, rst is held low until the reset timer times out. clock selection pin (clksel) this pin sets the clksyn pin as either an oscillator output or a synchronization input pin. the clksel pin is also used for the i 2 c address selection. clock synchronization pin (clksyn) oscillator output/synchronization input pin. table 5. operating mode selection en1 en2 operating mode 0 0 regulators disabled 0 1 standard power sequencing 1 0 inverted power sequencing 1 1 no power sequencing, regulators enabled
analog integrated circuit device data 18 freescale semiconductor 34701 functional description functional internal block description functional internal block description introduction the 34701 incorporates a high performance synchronous buck regulator, supplying the microprocessor?s core, and a low dropout (ldo) linear regulator providing the microprocessor i / o and bus voltages. this device incorporates many advanced features; e.g., precisely maintained up / down power sequencing, ensuring the proper operation and prot ection of the cpu and power system. figure 11. 34701 functional internal block diagram boost regulator a boost regulator provides a high-voltage necessary to properly drive the buck regulator power mosfets, especially during the low input voltage condition. the ldo regulator external n-channel mosfet gate is also powered from the boost regulator. in order to properly enhance the high side mosfets when only a +3.3v supply rail powers the integrated circuit, the boost regulator provides an output voltage of 7.75v nominal value. the 34701 boost regulator uses a simple hysteretic current control technique, which allows fast power-up and does not require any compensation. when the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. after the inductor current reaches the upper current limit (nominally set at 1.0a), the low-side switch is turned off and the current charges the output capacitor through the internal rectifier. when the inductor current falls below the valley current limit value (nominally 600ma), the low side switch is turned on again, starting the next switching cycle. after the boost regulator output capacitor reaches approximately 6.0 volts, the peak and valley current limit levels are proportionally scaled down to approximately one fifth of their original values. when the boost regulator reaches its regulation limit (7.75v typical), the low side switch is turned off until the output voltage falls below the regulation limit again. the higher current limit values in the beginning of the boost regulator start-up sequence allow fast power up of the whole ic, while the normal operation with reduced current limit greatly reduces the switching noise and therefore improves the overall emc performance. see figure 12 for the boost regulator output voltage and inductor current waveforms (picture not to scale). boost regulator reset control vddi power sequencing i 2 c interface voltage margining internal bandgap voltage thermal shutdown switcher uvlo buck control logic linear regulator i lim buck hs and ls driver control oscillator 300khz watchdog timer reference supply por timer bandgap voltage reference
analog integrated circuit device data freescale semiconductor 19 34701 functional description functional internal block description figure 12. boost regulator startup (not to scale) switching regulator the switching regulator is a high frequency (300khz default, adjustable in the range from 200khz to 400khz), synchronous buck converter driving integrated high side and low side n-channel power mosfets. the switching regulator output voltage is adjustable by means of an external resistor divider to provide the required output voltage within 2.0% accuracy, and is intended to directly power the core of the microprocessor. the buck controller uses a pwm voltage mode control topology with feed-forward to achieve excellent line and load regulation. the 34702 integrated boost regulator provides a 7.75v rail which is used to properly bias the switcher?s mosfet. in addition, the boost structure has a very low start-up voltage (typically 1.6v), hence ensuring very low input voltage functionality. a typical bootstrap technique is used to provide voltage necessary to properly enhance the high side mosfet gate. when the regulator is supplied only from low input voltage (e.g., single +3.3v supply rail), the bootstrap capacitor is charged from the internal boost regulator output v bst through an external diode. this arrangement allows the 34701 to operate from very low input voltage and also comply with the power sequencing requirements of the supplied microcontroller. figure 13. switching regulator current limit (not to scale) to avoid destruction of the supplied circuits, the switching regulator has a current limit wi th retry capability. when an over-current condition occurs and the switch current reaches the peak current limit value, the main (high side) switch is turned off until the inductor current decays to the valley value, which is one half of the peak current limit. if an over-current condition exists for 10ms, the buck regulator control circuit shuts the switcher off and the switcher retry timer starts to time out. when the timer expires after 100ms, the switcher engages the start-up sequence and runs for 10ms, repeatedly checking for the over-current condition. figure 13 describes the switching regulator over-current condition and current limit. during the current limited operation (e.g., in case of short-circuit on the switching regulator output), the switching regulator operation is not synchronized to the oscillator frequency. figure 14 (respectively figure 15 ) depicts the current limit with a retry capability feature of the switcher (respectively ldo). figure 14. switching converter over-current protection 6.0 v 7.7 5 v i pk =1atyp. 0.6 a typ . 0.2 a t yp. 0.1 a typ . booster output voltage 0v bo ost er ind u ct or current i pk 0.5 i pk t fa u l t =10ms cu rrent limit i pk 0.5 i pk t fault =10ms 0a t ret =100ms fault timer retry timer
analog integrated circuit device data 20 freescale semiconductor 34701 functional description functional internal block description figure 15. ldo converter over-current protection the output voltage vout can be adjusted by means of an external resistor divider connected to the feedback control pin inv. the switching regulator output voltage can be adjusted in the range of 0.8v to v in - buck dropout voltage. power-up, power-down, and fault management are coordinated with the linear regulator. switcher oscillator a 300khz (default) oscillator sets the switching frequency of the buck regulator. the frequency of the oscillator can be adjusted between 200khz and 400khz by an optional external resistor r f connected from the freq pin of the integrated circuit to ground. see figure 6 on page 14 for frequency resistor selection. the clksyn pin can be configured as either an oscillator output when the clksel pin is left open or as a synchronization input when the clksel pin is grounded. the oscillator output signal is a square wave logic signal with 50% duty cycle, 180 degrees out-of-phase with the internal clock signal. this allows opposite phase synchronization of two 34702 devices. when the clksyn pin is used as a synchronization input (clksel pin grounded), th e external resistor r f chosen from the chart in figure 6 should be used to synchronize the internal slope compensation ramp to the external clock. operation is only recommended between 200khz and 400khz. the supplied synchronization signal does not need to be 50% duty cycle. minimum pulse width is 1.0s. low dropout linear regulator (ldo) the adjustable low dropout linear regulator (ldo) is capable of supplying a 1.0a output current. it has a current limit with retry capability. when the voltage measured across the current sense resistor reaches the 50mv threshold, the control circuit limits the current for 10ms. if the over-current condition still exists, the linear regulator is turned off and the retry timer starts to time out. when the timer expires after 100ms, the ldo tries to power-up again for 10ms, repeatedly checking for the over-current condition. the current limit of the ldo can be set by using the following formula: i lim = 50mv / rs where r s is the ldo current sense resistor, connected between the cs pin and the ldo pin output (see figure 33 on page 34 ), and 50mv is the typical value of the ldo current sense comparator threshold voltage. when no current sense resistor is used, it is still possible to detect the over-current condition by tying the current sense pin cs to the vbst voltage. in this case, the over-current condition is sensed by saturation of the linear regulator driver buffer. the output voltage of the ldo can be adjusted by means of an external resistor divider connected to the feedback control pin lfb. the linear regulator output voltage can be adjusted in the range of 0.8v to v in - ldo dropout voltage. power-up, power-down, and fault management are coordinated with the switching regulator. power sequencing voltage margining watchdog timer a watchdog function is available via i 2 c bus communication. it is possible to select either window watchdog or timeout watchdog operation, as illustrated in figure 16 . watchdog timeout starts when the watchdog function is activated via i 2 c bus sending a watchdog programming command byte, thus determining watchdog operation (window or timeout) and period duration (refer to table 8 , page 27 ). if the watchdog is cleared by receiving a new watchdog programming command through the i 2 c bus, the watchdog timer is reset and the new timeout period begins. if the watchdog time expires, the rst will become active (low) for a time determined by the rc components of the rt timer plus 10ms. after a watchdog timeout, the function is no longer active. figure 16. watchdog operation 50% of watchdog period watchdog period timing selected via 12c bus ? see table 4 watchdog closed no watchdog clear allowed window open for watchdog clear window open for watchdog clear watchdog period timing selected via i 2 c bus ? see table 4 window watchdog time-out watchdog
analog integrated circuit device data freescale semiconductor 21 34701 functional description functional internal block description when the window watchdog function is selected, the timer cannot be cleared during the closed window time, which is 50% of the total watchdog period. when the watchdog is cleared, the timer is reset and starts a new tim-out period. if the watchdog is not cleared during the open window time, the rst will become active (low) for a time determined by the rc components of the rt timer plus 10ms.
analog integrated circuit device data 22 freescale semiconductor 34701 functional device operation operational modes functional device operation operational modes thermal shutdown to increase the overall safety of the system designed with the 34701, an internal thermal shutdown function has been incorporated into the switching regulator circuit. the 34701 senses the temperature of the buck regulator main switching mosfet (high side mosfet m1; see figure 2 on page 2 ), the low side (synchronous mosfet m2), and control circuit. if the temperature of any of the monitored components exceeds the limit of safe operation (thermal shutdown), the switching regulator and the ldo shut down. after the temperature falls below the value given by the thermal shutdown hysteresis window, the switcher tries again to operate. the v out pull-down mosfet m3 has an independent thermal shutdown control. if the m3 temperature exceeds the thermal shutdown, the m3 is turned off without affecting the switcher operation. the ldo pull-down mosfet m4 has an independent thermal shutdown control. if the m4 temperature exceeds the thermal shutdown, the m4 will be turned off without affecting the ldo operation. soft start a switching regulator soft start feature is incorporated in the 34701. the soft start is active each time the ic is enabled, vin is reapplied, or after a fault retry. other transient events do not activate the soft start. voltage margining the 34701 includes a voltage margining feature accessed through the i 2 c bus. voltage margining allows for independent adjustment of the switcher v out voltage and the linear output v ldo . each can be adjusted up and down in 1.0% steps to a range of 7.0%. this feature allows for worst case system va lidation; i.e., dete rmining the design margin. margining details are described in the section entitled i 2 c bus operation, beginning on page 26 of this datasheet. power sequencing modes the power sequencing of the two outputs of this power supply ic is in compliance with the freescale power quicc and other 32-bit microprocessor requirements. when the input voltage is applied, the switcher and linear regulator outputs follow the supply rail voltage during power-up and power-down in the limits given by the microcontroller power sequencing specification, illustrated in figures 17 through 19 . there are two possible power sequencing modes, standard and inverted, as explained in more detail below. the third mode of operation is power sequencing disabled. figure 17. standard power-up / down sequence in +3.3v supply system ? v = 2.1 v max. lead ? v = 0.4 v max. lag ? v = 2.1 v max. lead slope 1.0 v/ms 1.8v start-up 3.3 v input supply (i/o voltage) 1.5 v core voltage other circuits rt vbd vddl (core) vddh (i/os) mcu 34701 3.3 v input vin2 clksel freq gnd sda scl 2.5 v addr vin1 ldrv ldo lfb cs rst sw pgnd inv vbst boot vout clksyn optional en1 en2 vbst vddi 3.3 v 1.5 v
analog integrated circuit device data freescale semiconductor 23 34701 functional device operation operational modes figure 18. standard power-up / down sequence in +5.0v supply system standard power sequencing when the power supply ic operates in the standard power sequencing mode, the switcher output provides the core voltage for the microprocessor. this situation and operating conditions are illustrated in figures 17 and 18 . table 5 , page 17 , shows the power sequencing mode selection. inverted power sequencing when the power supply ic is operating in the inverted power sequencing mode, the linear regulator (ldo) output provides the core voltage for the microprocessor, as illustrated in figure 19 . table 5 shows the power sequencing mode selection. figure 19. inverted power-up / down sequence in +5.0v supply system assumed requirements 1. i/o supply voltage not to exceed core voltage by more than 2.0v. 2. core supply voltage not to exceed i/o voltage by more than 0.4v. methods of control the 34701 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. power sequencing control is also achieved through the intrinsic operation of the regulators. the en1 and en2 pins can be used to select the proper power sequencing mode required by the powered system or to disable the power sequencing (refer to table 5 ). intrinsic operation for both the ldo and switcher, whenever the output voltage is below the regulation point, the ldo external pass mosfet is on, or the buck high side mosfet is on at a duty cycle controlled by th e switcher. because these devices are mosfets, current can flow in either direction, balancing the voltages via the common supply pin. the ability to maintain the mosfets on is dependent on the available gate voltage, and thus the size of the boost regulator storage capacitor. ? v = 2.1 v max. lead ? v = 0.4 v max. lag ? v = 0.4 v max. lag 1.8v start-up 3.3 v i/o voltage (vldo) 1.5 v core voltage (vout) 5.0 v input supply ? v = 2.1 v max. lead rt vbd vddh (i/os) vddl (core) mcu 34701 5.0 v input vin2 clksel freq gnd sda scl addr vin1 ldrv ldo lfb cs rst sw pgnd inv vbst boot vout clksyn optional en1 en2 vbst vddi 3.3 v 1.5 v 5.0 v ? v = 2.1 v max. lead ? v = 0.4 v max. lag ? v = 0.4 v max. lag 1.8v start-up 3.3 v i/o voltage (vout) 1.5 v core voltage (vldo) 5.0 v input supply ? v = 2.1 v max. lead rt vbd vddh (i/os) vddl (core) mcu 34701 5.0 v input vin2 clksel freq gnd sda scl addr vin1 ldrv ldo lfb cs rst sw pgnd inv vbst boot vout clksyn optional en1 en2 vbst vddi 3.3 v 1.5 v 5.0 v
analog integrated circuit device data 24 freescale semiconductor 34701 functional device operation operational modes standard power se quencing control comparators monitor voltage differences between the ldo (ldo pin) and the switcher (vout pin) outputs as follows: 1. ldo > vout + 1.9v, turn off ldo. the ldo can be forced off. this occurs whenever the ldo output voltage exceeds the switcher output voltage by more than 1.9v. 2. ldo > vout + 2.0v, shunt ldo to ground. if turning off the ldo is insufficient and the ldo output voltage exceeds the switcher output voltage by more than 2.0v, a 1.5 ? shunt mosfet is turned on that discharges the ldo load capacitor to ground. the shunt mosfet is used for switcher output shorts to ground and for power down in case of vin1 vin2 with the switcher output fa lling faster than the ldo. 3. ldo < vout + 1.9v cancel (2). 4. ldo < vout + 1.8v, cancel (1) above, re-enable ldo. normal operation resumes when the ldo output voltage is less than 1.8v above the switcher output voltage. 5. ldo < vout - 0.1v, turn off switcher. the switcher can be forced off. this occurs whenever the ldo is less than vout - 0.1v. 6. ldo < vout - 0.3v, turn on sync (ls) mosfet and 1.5 ? vout sink mosfet. the buck high side mosfet is forced off and the sync mosfet is forced on. this occurs when the switcher output voltage exceeds the ldo output by more than 300mv. 7. ldo > vout - 0.3 v, cancel (6). 8. ldo > vout - 0.1v, cancel (5). normal operation resumes when ldo < vout - 0.1 v . inverted power sequencing control comparators monitor voltage differences between the switcher (vout pin) and ldo (ldo pin) outputs as follows: 1. vout > ldo + 1.8v, turn off vout . the switcher vout can be forced off. this occurs whenever the vout output voltage exceeds the ldo output voltage by more than 1.8v. 2. vout > ldo + 2.0v, shunt vout to ground. if turning off the switcher vout is insufficient and the vout output voltage exceeds the ldo output voltage by more than 2.0v, a 1.5 ? shunt mosfet and the switcher synchronous mosfet are turned on to discharge the vout load capacitor to ground. the shunt mosfet and synchronous mosfet are used for ldo output shorts to ground and for power down in case of vin1 vin2 with ldo output falling faster than the vout . 3. vout < ldo + 1.8v, cancel (1) and (2) above, re- enable vout . normal operation resumes when the vout output voltage is less than 1.8v above the ldo output voltage. 4. vout < ldo + 2.0 v, cancel (2) 5. vout < ldo - 0.2v, turn off ldo. the ldo can be forced off. this occurs whenever the vout is less than vldo - 0.2v. 6. vout < ldo - 0.3v, turn on the 1.5 ? ldo sink mosfet. this occurs when the ldo output voltage exceeds the vout output by more than 300mv. 7. vout < ldo - 0.2 v, cancel (6). 8. vout < ldo - 0.1v, cancel (5). normal operation resumes when vout > ldo - 0.1 v . standard operating mode single 3.3v supply, vi n = vin1 = vin2 = 3.3v the 3.3v supplies the microprocessor i/o voltage, the switcher supplies core voltage (e.g., 1.5v nominal), and the ldo operates independently (see figure 17 , page 22 ). power sequencing depends only on the normal switcher intrinsic operation to control the buck high side mosfet. power-up when vin is rising, initially vout is below the regulation point and the buck high-side mosfet is on. in order not to exceed the 2.1 v differential requirement between the i/o (vin) and the core (vout), the switcher must start up at 2.1 v or less and be able to maintain the 2.1 v or less differential. the maximum slew rate for v in is 1.0 v/ms. power-down when vin is falling, vout falls below the regulation point; therefore, the buck high side mosfet is on. in the case where vout is falling faster than vin, the buck high side mosfet attempts to maintain vout. in the case where vin is falling faster than vout, the buck high side mosfet is also on, and the vout load capacitor is discharged through the buck high side mosfet to vin. thus, provided vin does not fall too fast, the core voltage (vout) does not exceed the i/o voltage (vin) by more than a maximum of 0.4v. shorted load 1. vout shorted to ground. this causes the i/o voltage to exceed the core voltage by more than 2.1v. no load protection. 2. vin shorted to ground. until the switcher load capacitance is discharged, the core voltage exceeds the i/o voltage by more than 0.4v. by the intrinsic operation of the switcher, the load capacitor is discharged rapidly through the buck high side mosfet to vin. 3. vout shorted to supply. no load protection. 34701 is protected by current limit and thermal shutdown.
analog integrated circuit device data freescale semiconductor 25 34701 functional device operation operational modes single 5.0v supply, vin1 = vin2, or dual supply vin1 vin2 the ldo supplies the microprocessor i/o voltage. the switcher supplies the core (e.g., 1.5v nominal) (see figure 18 , page 23 ). power-up this condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the vin1 and vin2 supplies. there are two cases: 1. ldo rises faster than vout . the ldo uses control methods (1) and (2) described in the section methods of control on page 23 . 2. vout rises faster than ldo. the switcher uses control methods (5) and (6) described in the section methods of control on page 23 . power-down this condition depends upon the regulator load current and capacitance and the relative fall times of the vin1 and vin2 supplies. there are two cases: 1. vout falls faster than ldo. the ldo uses control methods (1) and (2) described in the section methods of control on page 23 . in the case vin1 = vin2, th e intrinsic operation turns on both the buck high side mosfet and the ldo external pass mosfet, and discharges the ldo load capacitor into the vin supply. 2. ldo falls faster than vout . the switcher uses control methods (5) and (6) described in the section methods of control on page 23 . shorted load 1. vout shorted to ground. the ldo uses method (1) and (2) described in the section methods of control on page 23 . 2. ldo shorted to ground. the switcher uses control methods (5) and (6) described in the section methods of control on page 23 . 3. vin1 shorted to ground. device is not working. 4. vin2 shorted to ground with vin1 and vin2 different. this is equivalent to the switcher output shorted to ground. 5. vout shorted to supply. no load protection. 34701 is protected by current limit and thermal shutdown. 6. ldo shorted to supply. no load protection. 34701 is protected by current limit and thermal shutdown. inverted operating mode single 3.3v supply, vi n = vin1 = vin2 = 3.3v the 3.3v supplies the microprocessor i/o voltage, the ldo supplies core voltage (e.g., 1.5v nominal), and the switcher vout operates independently. power sequencing depends only on the normal ldo intrinsic operation to control the pass mosfet. power-up when vin is rising, initially ldo is below the regulation point and the pass mosfet is on. in order not to exceed the 2.1v differential requirement between the i/o (vin) and the core (ldo), the ldo must start up at 2.1v or less and be able to maintain the 2.1v or less differential. the maximum slew rate for v in is 1.0v/ms. power-down when vin is falling, ldo falls below the regulation point; therefore, the pass mosfet is on. in the case where ldo is falling faster than vin, the pass mosfet attempts to maintain ldo. in the case where vin is falling faster than ldo, the pass mosfet is also on, and the ldo load capacitor is discharged through the pass mosfet to vin. thus, provided vin does not fall too fast, the core voltage (ldo) does not exceed the i/o voltage (vin) by more than maximum of 0.4v. shorted load 1. ldo shorted to ground. this will cause the i/o voltage to exceed the core voltage by more than 2.1v. no load protection. 2. vin shorted to ground. until the ldo load capacitance is discharged, the core voltage exceeds the i/o voltage by more than 0.4v. by the intrinsic operation of the ldo, the load capacitor is discharged rapidly through the pass mosfet to vin. 3. ldo shorted to supply. no load protection. single 5.0v supply, vin1 = vin2, or dual supply vin1 vin2 the switcher vout supplie s the microprocessor i/o voltage. the ldo supplies the core (e.g., 1.5v nominal) (see figure 19 , page 23 ). power-up this condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the vin1 and vin2 supplies. there are two cases: 1. vout rises faster than ldo. the switcher vout uses control methods (1) and (2) described in the section methods of control on page 23 . 2. ldo rises faster than vout . the ldo uses control methods (5) and (6) described in the section methods of control on page 23 . power-down this condition depends upon the regulator load current and capacitance and the relative fall times of the vin1 and vin2 supplies. there are two cases:
analog integrated circuit device data 26 freescale semiconductor 34701 functional device operation operational modes 1. ldo falls faster than vout . the vout uses control methods (4) and (5) described in the section methods of control on page 23 . in the case vin1 = vin2, th e intrinsic operation turns on both the buck high side mosfet and the ldo external pass mosfet, and discharges the vout load capacitor into the vin supply. 2. vout falls faster than ldo. the ldo uses control methods (5) and (6) described in the section methods of control on page 23 . shorted load 1. ldo shorted to ground. the vout uses methods (1) and (2) described in the section methods of control on page 23 . 2. vout shorted to ground. the ldo uses control methods (5) and (6) described in the section methods of control on page 23 . 3. vin1 shorted to ground. device is not working. 4. vin2 shorted to ground. this is equivalent to the switcher v out output shorted to ground. 5. ldo shorted to supply. no load protection. 34701 is protected by current limit and thermal shutdown. 6. vout shorted to supply. no load protection. 34701 is protected by current limit and thermal shutdown. logic commands and registers i 2 c bus operation the 34701 device is compatible with the i 2 c interface standard. sda and scl pins are the serial data and serial clock pins of the i 2 c bus. i 2 c command and data formats communication start communication starts with a start condition, followed by the slave device unique address. the read/write (r/w) bit defines whether the data should be read from or written to the device (the 34701 operates only as a slave device; therefore, the r/w bit should always be set to 0). the 34701 responds by sending the acknowledge bit (ack) to the master device. figure 20 illustrates the beginning of an i 2 c communication for a 7-bit slave address. figure 20. communication start using 7-bit address slave address definition 34701 has the two least significant address bits (lsb) defined by the state of the clksel pin (a1) and the addr pin (a0). note the state of the clksel pin also defines the configuration of th e oscillator synchroni zation clksyn pin. leaving the clksel pin open or pulling it hi gh defines the clksyn pin as an oscillator output. when the clksel pin is pulled low, the clksyn pin is configured as a synchronization input for the external clock signal. this feature allows up to four 34701 ics to communicate in the same i 2 c bus, all of them sharing the same high order address bits. a different combination of the two lsb address bits a1 and a0 can be assigned to each individual part to assure its unique address. figure 21 illustrates the flexible addressing feature for a 7-bit address. table 6 provides the definition of the selectable portion of the device address. when the addr pin is used and put to low level, pull the addr pin to ground through a 10k ? resistor. figure 21. address bit de finition for 7-bit address writing data into the slave device after the address acknowledgment by the slave, data can be written into the slave registers. the r/w bit must be set to 0 to allow data to be written into the 34702. figure 22 shows the data write sequenc e. actions performed by the slave device are grayed. figure 22. data transfer for write operations s 7-bit address r/w ack table 6. definition of selectable portion of device address clksel pin addr pin a1 a0 low low 0 0 low high (open) 0 1 high (open) low 1 0 high (open) high (open) 1 1 bits fixed address selectable address 10 2 3 5 6 11101 a1 a0 4 msb lsb s 7-bit address 0ack data ack (write)
analog integrated circuit device data freescale semiconductor 27 34701 functional device operation operational modes data definition the data field in the single data transfer contains one or several command bytes. the command byte identifies the kind of operation required by the master to be performed and has two fields, as illustrated in figure 23 : 1. address field 2. value field the address field is selected from the list in table 7 . figure 23. command byte refer to table 8 , page 27 , which summarizes the value field definitions for the entire set of operation options. security in writing commands to improve the security level, a so-called first command is defined to initiate each write communications. the first command identifies the operation, which is executed by the following command byte. a first command has the address field equal to the related operation one, followed by a null value field (all zeros). table 9 summarizes first command definitions. the master sends the first command before the command byte for the intended operation. voltage margin ing operation after starting the communication in writing mode, the master sends the first command followed by the specific command byte to set the required voltage margining for either the ldo or the switcher (see figure 24 ). to achieve a simultaneous set for both ldo and switcher, two specific commands must be issued in sequence after the first command, one for each supply. table 7. address field definitions address field operation write 001 voltage margining w 011 watchdog w table 8. command byte definitions operation address value action voltage margining (as a 2nd command byte) 001000001st command 001x0000 output nominal 001x0001 + 1.0% 001x0010 + 2.0% 001x0011 + 3.0% 001x0100 + 4.0% ldo output: x = 0001x0101 + 5.0% switcher output x = 1 001x0110 + 6.0% 001x0111 + 7.0% 001x1000 - 1.0% 001x1001 - 2.0% 001x1010 - 3.0% 001x1011 - 4.0% 001x1100 - 5.0% 001x1101 - 6.0% 001x1110 - 7.0% d6 d5 d4 d3 d1 d0 address field value field 7 d7 d2 3210 4 5 6 bits msb lsb watchdog programming (as a 2nd command byte) 011000001st command 01100000 wd off (24) 01101000 wd 1280ms wind. off 01101001 wd 320ms wind. off 01101010 wd 80ms wind. off 01101011 wd 20ms wind. off 01101100 wd 1280ms wind. on 01101101 wd 320ms wind. on 01101110 wd 80ms wind. on 01101111 wd 20ms wind. on notes 24. the watchdog timer is turned on automatically after receiving any other valid command byte changing watchdog time. table 9. first command definitions first command operation 001 00000 voltage margining 011 00000 watchdog programming table 8. command byte definitions
analog integrated circuit device data 28 freescale semiconductor 34701 functional device operation operational modes figure 24. voltage margining programming (one supply only) note: x bits, which set the voltage margining value are defined in table 8 . watchdog programming operation for watchdog operation control, the master periodically sends a watchdog first command followed by a command byte selecting, or confirming, the watchdog period according to the options listed in table 8 . see figure 25 for the watchdog timer programming command example. the internal watchdog timer is turned on by receiving a valid watchdog programming command (after receiving the watchdog programming first command), and it is cleared each time the next watchdog programming command is written into the device, provided it arrives during the window open time. thus, the watchdog programming command clears the timer and sets the new timing conditions at the same time. the watchdog programming first command 01100000 sent twice shuts the timer off, and the watchdog function is disabled. any other valid watchdog command turns the timer on again. figure 25. watchd og timer programming note: x bits, which set the watchdog timer value are defined in table 8 , page 27 . communication stop only the master can terminate the data transfer by issuing a stop condition. the slave waits for this condition to resume its initial state waitin g for the next start condition (see figure 26 ). complete data transfer examples the master device controlling the i 2 c bus always starts addressing a 34701 slave ic in writing mode (r/w = 0) to enable it to write a command byte just after receiving the address acknowledge sent by 34702. i 2 c bus protocol defines this circumstance as a master-transmitter and slave- receiver configuration. figure 27 illustrates a communication beginning with the slave address, the first command for voltage margining, and a third byte containing the address field 001 and the value field 00101 corresponding with the ldo fifth setting (ldo output voltage = +5% above its nominal value). if a simultaneous setting for switcher is needed, a fourth byte should be included before the stop condition (p); for instance, 001 11100 to set the switcher in its twelfth setting (switcher output voltage = -5% below its nominal value) - see figure 28 . the example of data transfer setting the watchdog timer is shown in the figure 26 . figure 26. data transfer example - watch dog timer setting. figure 27. data transfer example - ldo voltage margining 00 00000 10 01 x x x x x first byte for voltage margining command byte ack 01 00000 11 01 x x x x x first byte for watchdog programming command byte ack start slave address write first command for watchdog programming address field value field: time-out wd = 320 ms stop p ack a6 a4 a0 0110 0 0ack 00 ack 0110 1001 s a5 a3 a2 a1 0 (window off) start slave address write first command for voltage margining address field value field = ldo 5th setting stop p ack a6 a4 a0 0010 0 0ack 00 ack 0010 0101 s a5 a3 a2 a1 0
analog integrated circuit device data freescale semiconductor 29 34701 functional device operation operational modes figure 28. data transfer example - ldo and switcher voltage margining start slave address write first command for voltage margining address field value field: ldo ack a6 a4 a0 0010 0 0ack 00 ack 0010 0101 s a5 a3 a2 a1 0 address field value field: switcher v out = nom. - 5% stop p ack 0011 1100 v ldo = nom. + 5%
analog integrated circuit device data 30 freescale semiconductor 34701 typical applications typical applications buck regulator control circuit the 34701 buck regulator utilizes a pwm voltage mode topology with feed-forward to achieve an excellent line and load regulation. the control circuit block diagram is shown in figure 29 . figure 29. buck regulator control circuit the integrated 40pf capacitor c f charged through the external resistor r4 prov ides the feed-forward ramp waveform, the amplitude of which is proportional to the input voltage, thus providing the feed-forward function. figure 30 shows the bode plot of the 34701 buck regulator control loop gain and phase versus frequency. the first double pole on the bode plot is created by the buck regulator output l-c filter, and its frequency can be calculated as: where c o is the value of the buck output capacitor and l is the inductance value of the output filter inductor l. the frequency of the compensating zero can be calculated as follows. the feed-forward implemented by resistor r4 and integrated capacitor c f creates a pole in the overall loop transfer function, the frequency of which can be calculated from the following formula. where v ref is the buck regulator reference voltage (v ref = 0.8v typ.) at the inv pin, v in is the buck regulator input voltage, v m1 is the ramp generated by the internal ramp generator (v m1 = 0.5v typ.). l f lc 1 2 c o l ---------------------- = f zc () 1 2 c2 r1 r3 + () ---------------------------------------- = f pff () v in 1 f sw ------- v in v ref ? () r4c f -------------------------------- v m1 + ---------------------------------------------------------------- 1 2 r4c f --------------------- =
analog integrated circuit device data freescale semiconductor 31 34701 typical applications . figure 30. buck control loop bode plot the frequency of the zero created by the esr of the output capacitor c o is calculated as: where c o is the value of the buck regulator output capacitor, and esr is the equivalent series resistance of the output capacitor. the frequency of the compensating network pole can be calculated as follows: the well designed and compensated buck regulator should yield at least 45 deg. phase margin m of its overall loop as depicted in the figure 30 , page 31 . selecting buck regulator output voltage the 34701 buck regulator output voltage can be set by selecting the right value of the resistors r1, r2 and r4, and can be determined from the following formula (see figure 29 , page 30 for the component references): where v ref is the buck regulator reference voltage (v ref = 0.8v typ.) at the inv pin, v o is the selected output voltage, i o is the output load current, r l is the dc resistance of the inductor l. it is apparent that the buck regulator output voltage is affected by the voltage drop caused by the inductor serial resistance and the regulator output current. in those applications which do not require precise output voltage, setting the formula for calculating selected output voltage can be simplified as follows: linear regulator output voltage the output voltage of the linear regulator (ldo) can be set by a simple resistor divider according to the following formula: where v ref is the linear regulator reference voltage (v ref = 0.8v typ.) at the lfb pin, v ldo is the ldo selected output voltage, r u is the ?upper? resistor of the ldo resistor divider, r l is the ?lower? resistor of the ldo resistor divider. figure 31 describes the 34701 linear regulator circuit with the resistor divider r u , r l setting the output voltage v ldo . figure 31. 34701linear regulator circuit m 0 -20 20 -40 -2 70 -3 60 -180 10 100 1000 1.0 frequency [khz] gain [db] f lc f z(c) f bw f z(e sr) f p(ff) f p(c) 1000 0 pha se [deg.] f zesr () 1 2 c o esr -------------------------- = f pc () 1 2 c2 r1r3 r1 r3 + () ------------------------- ---------------------------------------- = r2 v ref 1 v o i o r l + () v ref ? r4 ------------------------------------------------------- - v o v ref ? r1 ------------------------- + ---------------------------------------------------------------------------------------- - = r2 v ref 1 v o v ref ? () r1 r4 + () r1 r4 ------------------------- -------------------------------------------------------------- - = v ldo v ref 1 r u r l ------- + ?? ?? = ldrv ldo lf b cs mc34701 2.8 v to 6.0 v input vin1 r s r u r l c ldo v ldo lcmp ldo compensation
analog integrated circuit device data 32 freescale semiconductor 34701 typical applications linear regulator current limit as described in the linear regulator functional description section, the current limit of the linear regulator can be adjusted by means of an external current sense resistor r s . the voltage drop caused by the regulator output current flowing through the current sense resistor r s is sensed between the ldo and the cs pins. when the sensed voltage exceeds 50mv (typical), the current limit timer starts to time out while the control circuit limits the output current. if the over-current condition lasts for more than 10ms, the linear regulator is shut off and turned on again after 100ms. this type of operation provides equivalent protection to the analog ?current foldback? operation. it is important to keep in mind that the amount of capacitive load which can be supplied by the by the linear regulator is limited by the setting of the ldo current limit. during the power-up period, the linear regulator operates in the current limit, supplying the current into the load of the ldo, which includes all the capacitors connected to the regulator output. if the total amount load is so large that the regulator could not reach its regulation voltage in 10ms during the power-up, it turns off and tries to power up again after 100ms. this situation may lead to the power-up oscillations. linear regulator external mosfet the linear regulator uses an external n-channel power mosfet to provide a pass element for the power path. the selection of the proper type of the external power mosfet is critical for optimum performance and safe operation of the linear regulator. the power mosfet?s threshold voltage, r ds(on) , gate charge, capacitances and transconductance are important parameters for the stable operation of the linear regulator while the package of the power mosfet determines the maximum power dissipation, and hence the maximum output current for the required input-to-output voltage drop. the power dissipation of the external mosfet can be calculated from the simple formula: where p d(q) is the power mosfet power dissipation vin is the ldo input voltage, vldo is the ldo output voltage, ildo is the ldo output load current. table 10 shows the recommended power mosfet types for the 34701 linear regulator, their typical power dissipation, and thermal resistance junction-to-case. note : freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in figures or tables. although freescale offers component recommendations, it is the customer?s responsibility to validate their application. *when mounted to an fr4 using 0.5 sq.in. drain pad size the maximum power dissipation is limited by the maximum operating junction temperature t jmax . the allowed power dissipation in the given application can be calculated from the following expression: where p d(q)max is the power mosfet maximum allowed dissipation, t jmax is the power mosfet maximum operating junction temperature, t a is the ambient temperature, r thjc is the power mosfet thermal resistance junction-to-case, r thcb is the thermal resistance case-to-board, r thba is the thermal resistance board-to-ambient of the pc board. pcb layout considerations as with any power application, the proper pcb layout plays a critical role in the overall power regulator performance. while good careful printed circuit board layout significantly improves regulation parameters and electromagnetic compatibilit y (emc) performance of the switching regulator, poor layout practices can lead not only to significant degradation of regulation and emc parameters, but even to total dysfunction of the whole regulator ic. extreme care should be taken when laying out the ground of the regulator circuit. in order to avoid any inductive or capacitive coupling of the switching regulator noise into the sensitive analog control circuits, the noisy power ground and the clean quiet signal ground should be well separated on the printed circuit board, and connected only at one connection point. the power routing should be made by heavy traces or areas of copper. the power path and its return should be placed, if possible, atop each other on the different layers or opposite sides of the pc board. the switching regulator input and output capacitors should be physically placed very close to the power pins (vin2, sw, pgnd) of the 34701 switching regulator; and their ground pins, together with the 34701 power ground pins (pgnd), should be connected by a single island of the power ground copper to create the ?single-point? grounding. figure 32 illustrates the 34701 switching regulator grounding concept. the bootstrap capacitor c b should be tightly connected to the integrated circuit as well. table 10. recommended power mosfets part no. package typ. p d r thj-c irl2703s d2pak 2.0w 3.3c/w mtd20n03hdl dpak 1.75w* 1.67c/w p dq () i ldo v in v ldo ? () = p dq () max t jmax t a ? r thjc r thcb r thba ++ -------------------------------------------------------- -
analog integrated circuit device data freescale semiconductor 33 34701 typical applications figure 32. 34701 buck regulator layout the same guidelines as those for the layout of the main switching buck regulator should be applied to the layout of the low power auxiliary boost regulator and to some extent, the power path of the linear regulator. sw pgnd inv vou t = 1 .5 v gnd boot vbst vin2 cb vin=5.0v vout return signal ground power ground to l o a d
analog integrated circuit device data 34 freescale semiconductor 34701 typical applications figure 33. simplified block diagram and basic application 100 uf buck control logic + - + - thermal limit current limit error amp. pwm comp. uvlo vbst vddi sw freq power down reset control por timer syscon syscon inv en2 gnd 0.8v r b (2) en1 softst clksyn vin2 buck hs & ls driver vbst + - vref vref power enable 8.0v vbst boost control vbd 10uf vddi ldrv vref lfb cs ldo rt reset +3.3v supply voltage vddi r s sda scl ct pgnd reset r f 4.7 uh 10uh vin1 vin boot clksel vout vldo c b lcmp vbst l1 c o c in vref vddi q2 q1 (2) (2) (4) addr i 2 c interface rt i 2 c control i 2 c control c ldo 5 x 2.2 uf c bst d b q ldo l bst 0.1uf vddi r pd 10k vddi internal supply vddi bandgap voltage reference power sequencing voltage margining w-dog timer vbst ramp gen. vout to reset control pow. seq. switcher oscillator 300khz c in vbst linear regulator control i-lim vout 100pf 1.5k 2 x 22 uf 10uf 6.8nf 470pf 39k 300k 27k 300 (optional) 5.1k 100k 100nf 1.0 uf 0.022 r pow. seq. 4.7k 1.5k q3 q4 inv lfb + 100 uf buck control logic buck control logic + - + - + - + - thermal limit current limit error amp. pwm comp. uvlo vbst vddi sw freq power down reset control por timer syscon syscon inv en2 gnd 0.8v r b (2) en1 softst clksyn vin2 buck hs & ls driver buck hs & ls driver vbst + - + - vref vref power enable 8.0v vbst boost control boost control vbd 10uf vddi ldrv vref lfb cs ldo rt reset vddi r s sda scl ct pgnd reset r f 4.7 uh 10uh vin1 vin boot clksel vout vldo c b lcmp vbst l1 c o c in vref vddi q2 q1 (2) (2) (4) addr i 2 c interface rt i 2 c control i 2 c control c ldo 5 x 2.2 uf c bst d b q ldo l bst 0.1uf vddi r pd 10k vddi internal supply vddi bandgap voltage reference power sequencing voltage margining w-dog timer vbst ramp gen. ramp gen. vout to reset control pow. seq. switcher oscillator 300khz c in vbst linear regulator control i-lim linear regulator control i-lim vout 100pf 1.5k 2 x 22 uf 10uf 6.8nf 470pf 39k 300k 27k 300 (optional) 5.1k 100k 100nf 1.0 uf 0.022 r pow. seq. 4.7k 1.5k q3 q4 inv lfb + + 7.75v rst rst +3.3v supply voltage vout=1.8v vldo=3.3v @1.0a +3.3v or vldo to mcu q5 q6
analog integrated circuit device data freescale semiconductor 35 34701 typical applications figure 34. 34701 typical application circuit sda 1 q1 irl2703s or mtd20n03hdl c18 1.0uf optional r12 notes: c7 33nf c36 1.0uf u6 mc34701 3 4 5 6 7 10 11 8 9 12 13 14 17 26 15 16 18 19 20 21 22 27 28 25 2 29 30 31 32 1 23 24 vout vin2 vin2 sw sw pgnd pgnd gnd gnd vbd vbst boot lcmp addr sda scl lfb ldo cs ldrv vin1 en1 en2 gnd inv rt /reset clksel clksyn freq vddi gnd + c10 100uf optional 1. r11 can be adjusted according to the required ldo current limit. cs r13 4.7k 2. r12 = 16k for vout = 2.5v boot r18 2.2r r9 300r vin2 vin r17 1.5k c34 10nf r12 = 27k for vout = 1.8v. r11 0.022r scl 1 signal ground gnd 1 3. l1 = 4.7uh, do3316p-472hc from coilcraft vin2 c35 6.8nf d2 ll4148 reset 1 ldrv c23 10uf power ground c40 4.7nf or cdrh104r-4r7 from sumida. vbd 5 x 2.2 uf c37, l3 4. l2 = 10uh, slf6025t-100m1r3 from tdk r15 1.5k c40, r18 or 1812ps-103m from coilcraft. l1 4.7uh 1 2 lcmp r8 39k 7. c3, c10 = 100uf/6.3v, 10thb100ml poscap capacitor from sanyo. r1 10k l2 10uh 1 2 vcc5v 1 slf6025t c17 470pf clksyn 1 c2 10uf rlf7030-3r3m4r1 r4 10k vldo 1 5. l3 = 3.3uh, rlf7030-3r3m4r1 from tdk vout 1 c16 1.0uf boot + c37 10uf r2 5.1k r12 = 36k for vout = 1.5v. c39 1.0uf + c3 100uf l3 3.3uh 1 2 c33 10uf/16v 6. c2 = 10uf/10v, ceramic capacitor . 3.3v r19 510r c15 100nf c14 10nf r10 300k
analog integrated circuit device data 36 freescale semiconductor 34701 package dimensions package dimensions important: for the most current pa ckage revision, visit www.freescale.com and perform a ?keyword? search for the ?98a? number. ew suffix 32-pin 98aarh99137a revision b
analog integrated circuit device data freescale semiconductor 37 34701 package dimensions ew suffix 32-pin 98aarh99137a revision b
analog integrated circuit device data 38 freescale semiconductor 34701 revision history revision history revision date description of changes 5.0 2/2006 ? changed document order no. 6.0 2/2007 ? updated to the current freescale form and style. ? changed the status from advance information to final. ? added peak package reflow temperature during reflow (2) , (3) ? added notes (2) and (3) 7.0 8/2007 ? added MCZ34701ew/r2 to the ordering information ? updated the 98arh99137a package drawing to rev. b
mc34701 rev 7.0 8/2007 rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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